Springer, 2022. — 129 p. — ISBN 978-3-031-18396-6.
Обнаружение завершения в асинхронных схемах: на пути к решению проблем проектирования, связанных с часами
Asynchronous design style has experienced a renaissance in recent decades, as the demand for smaller, faster circuits exacerbates the challenges associated with clock distribution, clock skew and other clock-related issues in synchronous circuits.
Asynchronous circuits are inherently free from challenges associated with clock signals, as they do not use clock signal(s) to indicate the process completion and instead use handshaking signals to communicate between two asynchronous logic blocks. Using handshaking signals provides an opportunity for the designers of asynchronous circuits to determine the process completion based on the actual input data rather than having to wait for a critical path delay for each computation, as would be the case with a global clock. Hence, asynchronous circuits can utilise
the average-case computation delay as they have event-driven characteristics and can indicate data validity as soon as the computation is done, but detecting the completion of the computational process has always been a challenge in such circuits.
The key contributions of this book are as follows:• A generic architecture of deterministic completion detection scheme for bundled
data circuits
• Pallavi’s generic function Gp to deterministically detect the completion of ongoing computation process
• Reducing the computation delay of bundled data circuits from the worst-case delay to average-case delay with the help of the completion detection scheme, such that they can utilise the event-driven property of asynchronous circuits
• Implementing an adder and a barrel shifter using the proposed design to validate the generic architecture of the deterministic completion detection scheme with the help of the generic function Gp
1 Introduction to Asynchronous Circuit Design
2 Preliminary Considerations for Asynchronous Circuit Design
3 Completion Detection Schemes for Asynchronous Design Style
4 Case Studies: Barrel Shifter and Binary Adders
5 Generic Architecture of Deterministic Completion Detection Scheme
6 Architecture Optimisation Using Deterministic Completion Detection
7 Simulations
A Floating-Point Addition
B Shifter Test Bench