Maiti C.K. Computer Aided Design of Micro- And Nanoelectronic Devices

Singapore: World Scientific Publishing Company, 2016. — 455 p.The road towards enhancing the performance of integrated circuits comprises fundamental improvement of the devices via new structures, scaling the size and transistor features which increase its speed and reduce power consumption. Combination of new device architectures and use of strain-engineered materials have led towards nanoelectronic devices and pushed the limits of CMOS and BiCMOS scaling. Typical transistor gate lengths have reached 10 nm. The first processor built with the 14 nm technology is the Intel Core-M processor. At the beginning of 2015, the fifth generation Intel Core processor was released, which is also built with the 14 nm technology and with 1.3 billion transistors..
Computer aided design and simulation of transistors for upcoming technology nodes are the main focus of this book. The monograph address mainly the design issues of advanced CMOS and bipolar devices with technical depth and conceptual clarity and presents leading-edge device design solutions to address the new challenges presented by advanced technology nodes. The device design examples covered in this monograph are in use and provide useful technology and device physics insights. The purpose of this monograph is also to bring into one resource presenting a comprehensive perspective of advanced micro- and nanoelectronic device design using advanced simulation tools..
One major limitation of currently available books in related areas is that mostly the design and simulation results presented are using 2D simulators. Due to ultra-small size of the state-of-the-art devices, 3D effects have become dominant. In order to achieve a better understanding of simulated and fabricated device characteristics, 3D process/device simulation is essential. Also 3D integration has become one of the main directions to fit into device performance roadmaps.Dedication.List of Tables.
List of Figures.Simulation Tools.
Simulation Methodology.
CMOS Technology.
Stress-Engineered CMOS.
Heterojunction Bipolar Transistors.
Stress-Engineered HBTs.
FinFETs.
Advanced Devices.
Memory Devices.
Power Devices.
Solar Cells.
Heterojunction Solar Cells.
SPICE Parameter Extraction.