Figueiredo P.M., Vital J.C. Offset Reduction Techniques in High-Speed Analog-to-Digital Converters. Analysis, Design and Tradeoffs

Springer, 2009. — 290.The advent of CMOS technologies with lower feature sizes enables a sustained increase in the available memorization and processing capabilities, favoring the signal processing operations performed in digital domain. Quite often the signals to be processed are analog and, in some cases, must become analog after the digital processing. This requires the utilization of components that make the translation between the two domains: the Analog-to-Digital Converter (ADC) receives an analog signal and produces its binary coded representation; the Digital-to- Analog Converter (DAC) performs the opposite operation. Presently there are data converters in virtually all electronic systems: audio, video and imaging, communications, control, radar, etc.
The two most fundamental parameters of data converters are the sampling frequency (rate at which the input is examined and the corresponding output is produced), and the resolution (which determines the minimum analog signal amplitude that can be processed). Practical implementations indicate a primary tradeoff between these two parameters: data converters with higher sampling frequency have a smaller resolution.
There are several ADC architectures, each suited to a certain resolution/ sampling frequency range. This book focus on CMOS high-speed ADCs: the flash, two-step flash and folding and interpolation converters. These architectures (which currently achieve resolutions ranging from 6 to 10 bit, and sampling frequencies extending from 100 MHz to several GHz) and the tradeoffs in their constituting blocks are addressed in detail; furthermore, silicon implementations using all three architectures are presented.
These converters have the common characteristic of possessing subblocks that have no special linearity requirements, but whose offset voltages are of the upmost importance because they determine the overall ADC linearity. Offsets can be reduced by enlarging the components, but this increases the parasitic capacitances, leading to a larger power dissipation or to the reduction of the maximum operating frequency. The offset voltage is, in this way, the fundamental design parameter in high-speed CMOS analog-to-digital converters.
The utilization of offset reduction techniques is mandatory to achieve high frequency operation with low power dissipation and layout area. Averaging and offset sampling are the two most widely used and both are thoroughly examined and characterized. The most exhaustive study ever performed about averaging is, to the best knowledge of the authors, presented in this book. Also, previously proposed offset sampling methods are carefully reviewed to understand their limitations. Then two new techniques are proposed that, when combined, yield a nearly offset free comparator.
The research work published by the authors in leading IEEE transactions and conferences is detailedly presented and extended, resulting in a book that covers both the main high speed ADC architectures as well as the most widely used linearity improvement (offset reduction) techniques. This book is organized as follows.High-Speed ADC Architectures
Averaging Technique – DC Analysis and Termination
Averaging Technique – Transient Analysis and Automated Design
Integrated Prototypes Using Averaging
Offset Cancellation Methods
Conclusions
A: Averaging with Piecewise Linear Differential Pairs
B: Mismatches in the Resistors of the Averaging Network
C: Averaging in Folding Stages